Chapter 10 Memory Interface; Overview - Analog Devices adsp-2100 Manual

10.1

OVERVIEW

The ADSP-2100 family has a modified Harvard architecture in which data
memory stores data and program memory stores both instructions and
data. Each processor contains on-chip RAM and/or ROM, so that a
portion of the program memory space and a portion of the data memory
space reside on-chip. Each processor (except the ADSP-2181) also has a
boot memory space in addition to the data and program spaces. The
ADSP-2181 has a byte memory space instead of the boot memory space.
The boot memory space and byte memory space can be used to load on-
chip program memory with code from an external EPROM at reset.
In each ADSP-2100 family device, memory is connected with the internal
functional units by four on-chip buses: the data memory address bus
(DMA), data memory data bus (DMD), program memory address bus
(PMA), and program memory data bus (PMD). The internal PMA bus and
DMA bus are multiplexed into a single address bus which is extended off-
chip. Likewise, the internal PMD bus and DMD bus are multiplexed into a
single external data bus. The sixteen MSBs of the external data bus are
used as the DMD bus: external bus lines D
There are three separate memory spaces: data memory, program memory
and boot (or byte) memory. The
which memory space is being accessed. Because the program memory and
data memory buses are multiplexed off-chip, if more than one external
transfer must be made in the same instruction there will be an overhead
cycle required. There is no overhead if just one off-chip access (with no
wait states) occurs in any instruction. Figure 10.1 shows the external
memory buses and control signals (for all ADSP-21xx processors except
the ADSP-2181).
All external memories may have automatic wait state generation
associated with them. The number of wait states—each equal to one
instruction cycle—is programmable.
Memory Interface
PMS DMS
,
are used for DMD
23-8
BMS
, and signals indicate
10
.
15-0
10 – 1