Companding Operation Example - Analog Devices adsp-2100 Manual

5 Serial Ports
The ADSP-2100 family of processors supports both of the widely used
algorithms for companding: A-law and µ-law. The processor compands
data according to the CCITT G.711 recommendation. The type of
companding can be selected independently for each SPORT.
If companding is not enabled, there are two formats available for received
data words of fewer than 16 bits: one that fills unused MSBs with zeros,
and another that sign-extends the MSB into the unused bits.
The type of companding, as well as the non-companding data format, are
controlled by the DTYPE field (bits 5-4) in the SPORT control register
(0x3FF6 for SPORT0 and 0x3FF2 for SPORT1) as shown in Figure 5.22.
When companding is enabled, valid data in the RX0 or RX1 register is the
right-justified, sign-extended, expanded value of the eight LSBs received.
Likewise, a write to TX0 or TX1 causes the 16-bit value to be compressed
to eight LSBs (sign-extended to the width of the transmit word) before
being written to the internal transmit register. If the magnitude of the 16-
bit value is greater than the 13-bit A-law or 14-bit µ-law maximum, the
value is automatically compressed to the maximum positive or negative
value.

5.10.1 Companding Operation Example

With hardware companding, interfacing to a codec requires little
additional programming effort. See the codec hardware interfacing
example in the last section of this chapter.
Here is a typical sequence of operations for transmitting companded data:
• Write data to the TXn register
• The value in TXn is compressed
• The compressed value is written back to TXn
• After the frame sync signal has occurred (if required), TXn is written to
the internal transmit register and the bits are sent, MSB first.
As soon as the SPORT has started to send the second bit of the current
word, TXn can be written with the next word, even though transmission
of the first is not complete. After the MSB has been transferred, the SPORT
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