Analog Devices adsp-2100 Manual page 241

10 Memory Interface
ADSP-2100 family processors.
Figure 10.26 shows a memory design that provides full external program
and data memory overlays for an ADSP-2181 processor, assuming that
MMAP=0. The important points to note about this design are:
• Three 32K x 8-bit SRAMs are required for full external program and
data memory overlays; glue logic is not required.
• Four control lines are required for read (
CMS
(
• Composite Memory Select (CMSSEL) is configured to assert the
control line when Program Memory Select (
Select (
• The order of overlays stored in this design (from lowest address to
highest) is PM Overlay 1, PM Overlay 2, DM Overlay 1, and DM
Overlay 2. Address line 13 (A13) of the ADSP-2181 selects between
overlay 1 or 2. Figure 10.27 shows a memory map of this design.
ADDR 0 - 13
A0 - 13
CS
CMS
Figure 10.26 Example Program and Data Memory Overlay Design
10 – 28
), and data/program memory select (
DMS
) are asserted.
DATA 0 - 7
D0 - 7
32K x 8 BIT
SRAM
OE WE A14
RD WR PMS
RD
PMS
DATA 8 - 15
ADDR 0 - 13
A0 - 13 D0 - 7
32K x 8 BIT
SRAM
CS OE WE A14
CMS RD WR PMS
WR
), write ( ), chip select
DMS
or ).
PMS
) or Data Memory
ADDR 0 - 13
A0 - 13
32K x 8 BIT
SRAM
CS OE
CMS RD
CMS
DATA 16 - 23
D0 - 7
WE A14
WR PMS