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9
System Interface
Even though the processor is put into the powerdown mode, the lowest
level of power consumption still might not be achieved if certain
guidelines are not followed. Lowest possible power consumption requires
no additional current flow through processor output pins and no
switching activity on active input pins. Therefore, a careful analysis of pin
loading in your circuit is required. The following sections detail the
proper powerdown procedure as well as provide guidelines for clock and
output pin connections required for optimum low-power performance.
9.7.1
Powerdown Control
You can control several parameters of powerdown operation through
control bits in the SPORT1 Autobuffer/Powerdown Control Register
(or Analog Autobuffer/Powerdown Control Register on the
ADSP-21msp58/59). This control register is memory-mapped at location
0x3FEF and is shown in Figure 9.6.
SPORT1 Autobuffer / Powerdown Control Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DM(0x3FEF)
XTALDIS
XTAL Pin Drive Disable During Powerdown
1=disabled, 0=enabled
(XTAL pin should be disabled when
no external crystal is connected)
XTALDELAY
Delay Startup From Powerdown 4096 Cycles
1=delay, 0=no delay
(use delay to allow internal phase locked
loop or external oscillator to stabilize)
PDFORCE
Powerdown Force
1=force processor to vector to
powerdown interrupt
PUCR
Powerup Context Reset
1=soft reset (clear context)*,
0=resume execution
Figure 9.6 SPORT1 Autobuffer / Powerdown Control Register
* PUCR=1: Clears the PC, STATUS, LOOP and CNTR stacks. IMASK and ASTAT
registers are cleared to 0 and SSTAT is set to 0x55. The processor will start executing
instructions from address 0x0000.
9 – 18
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