Hip During Powerdown - Analog Devices adsp-2100 Manual

9 System Interface
If an external serial clock and an external frame sync signal are supplied,
data can be clocked into the RX register or out of the TX register during
powerdown. Since the TX register can not be updated while the processor
is in powerdown, the same value is repeatedly clocked out the serial port.
Also, data in the RX register is continually overwritten since the RX
register can not be read by the processor during powerdown.
If an external serial clock is used with an internal frame sync, frame sync
signals continue to be generated during powerdown since they are
derived from the serial clock. Data bits continue to be received with the
RX register being overwritten. Since data is only transmitted when the TX
register is written, data bits are only transferred out of the processor if the
processor is put in powerdown during a serial port transfer. While the
processor is being put into powerdown, the serial port transfer in progress
is allowed to complete. Since an internally generated transmit frame sync
is used, no subsequent frame syncs are generated while in powerdown.
If internal serial clock is used, there is no SPORT activity during
powerdown; the serial clock stops.
Lowest power dissipation is achieved when active SPORT pins are not
changing during powerdown and are held at CMOS levels.

9.7.5.3 HIP During Powerdown

The circuitry of the Host Interface Port (HIP) is not directly affected by
powerdown on the ADSP-2171 and ADSP-21msp58/59. The HIP is
indirectly affected since the processor, when in powerdown, is unable to
service interrupts or read and write HIP data registers. HIP circuitry
continues to operate during powerdown.
The host can write to the HIP register during powerdown but the
processor is disabled and cannot service interrupts. Instead, HIP
interrupts are latched and can be serviced if the processor exits
powerdown without a context reset (PUCR=1).
If the HDR overwrite bit (bit 7 in HSR7) is cleared, a host acknowledge
signal will not be asserted until the processor has read data written by the
host. During powerdown, the processor is unable to read the data register
and the host acknowledge signal will not be asserted. Care must be taken
in a system where the host waits for a host acknowledge. In this case, it is
possible that the host will "hang" waiting for the acknowledge while the
DSP processor is in powerdown.
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