Analog Devices adsp-2100 Manual page 79

CLKOUT
Interrupt
Instruction
Executing
Address for
Instruction Fetch
Figure 3.2 Interrupt Latency (Timer,
(Note that this latency for the timer interrupt only applies for the ADSP-2171,
ADSP-2181, and ADSP-21msp58/59 processors. See the next section for a
description of timer interrupt latency on the ADSP-2101, ADSP-2105,
ADSP-2115, ADSP-2111.)
For a pending interrupt that is masked, the latency from execution of the
instruction that unmasks the interrupt (in IMASK) to the first instruction of
the service routine is one cycle. This one-cycle latency is similar to that shown
in Figure 3.3 for the timer interrupt of the ADSP-2101/2105/2111/2115, with
the "n" instruction executing being the instruction that writes to IMASK (to
unmask the interrupt).
3.4.3.1 Timer Interrupt Latency on ADSP-2101, ADSP-2105, ADSP-2115, ADSP-2111
For the timer interrupt on these processors, the latency from when the
interrupt occurs to when the first instruction of the service routine is executed
is only one cycle. This is shown in Figure 3.3. The single cycle of latency is
needed to fetch the instruction stored at the interrupt vector location.
CLKIN
Timer
Value
Instruction
Executing
Address for
Instruction Fetch
Figure 3.3 Timer Interrupt Latency for ADSP-2101, ADSP-2105, ADSP-2115, ADSP-2111
Program Control
n–2 n–1
n–1 n
, SPORT, HIP, & Analog Interrupts)
IRQx x x x x IRQ IRQ IRQ IRQ
tcount=1
n NOP
interrupt
n+1
vector i
tcount=0
n NOP
interrupt
n+1
vector i
3
1st instr of
serv routine
i+1
1st instr of
serv routine
i+1
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