Load Register Immediate - Analog Devices adsp-2100 Manual

Syntax:
reg = <data> ;
dreg = <data> ;
data: <constant>
'%' <symbol>
'^' <symbol>
Permissible registers
dregs (Instruction Type 6)
(16-bit load)
AX0 MX0 SI
AX1 MX1 SE
AY0 MY0 SR1
AY1 MY1 SR0
AR MR2
MR1
MR0
Example:
I0 = ^data_buffer;
L0=%data_buffer;
Description:
Move the data value specified to the destination location.
The data may be a constant, or any symbol referenced with the "length of"
(%) or "pointer to" (^) operators. The data value is contained in the
instruction word, with 16 bits for data register loads and up to 14 bits for
other register loads. The value is always right-justified in the destination
location after the load (bit 0 maps to bit 0). When a value of length less than
the length of the destination is moved, it is sign-extended to the left to fill
the destination width.
Note that whenever MR1 is loaded with data, it is sign-extended into MR2.
For this instruction only, the RX and TX registers may be loaded with a
maximum of 14 bits of data (although the registers themselves are 16 bits
wide). To load these registers with 16-bit data, use the register-to-register
move instruction or the data memory-to-register move instruction with
direct addressing.
Status Generated:

LOAD REGISTER IMMEDIATE

None affected.
(instruction continues on next page)
regs (Instruction Type 7)
(maximum 14-bit load)
SB CNTR
PX OWRCNTR (write only)
ASTAT RX0
MSTAT RX1
IMASK TX0
ICNTL TX1
I0-I7 IFC(write only )
M0-M7
L0-L7
MOVE
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