Analog Devices adsp-2100 Manual page 189

9 System Interface
Control Field
Bus Exchange Register
PX
Status Registers
IMASK
ASTAT
MSTAT
SSTAT
ICNTL
IFC
Control Registers (memory-mapped)
BWAIT
BPAGE
SPORT1 configure
SPE0
SPE1
DWAIT0–4
PWAIT
TCOUNT
TPERIOD
TSCALE
Serial Port Control Registers (memory-mapped, one set per SPORT)
ISCLK
RFSR, TFSR
RFSW, TFSW
IRFS, ITFS
INVRFS, INVTFS
DTYPE
SLEN
SCLKDIV
RFSDIV
Multichannel word enable bits
MCE
MCL
MFD
INVTDV
RBUF, TBUF
TIREG, RIREG
TMREG, RMREG
FO (SPORT1 only)
Table 9.2 ADSP-2101/ADSP-2115 State After Reset Or Software Reboot
9 – 6
Description
PX register
Interrupt service enables
Arithmetic status
Mode status
Stack status
Interrupt control
Interrupt force/clear
Boot memory wait states
Boot page
Configuration
SPORT0 enable
SPORT1 enable
Data memory wait states
Program memory wait
Timer count register
Timer period register
Timer scale register
Internal serial clock
Frame sync required
Frame sync width
Internal frame sync
Invert frame sense
Companding type, format
Serial word length
Serial clock divide
RFS divide
Multichannel enable
Multichannel length
Multichannel frame delay
Invert transmit data valid
Autobuffering enable
Autobuffer I index
Autobuffer M index
Flag Out value
Reset Reboot
undefined undefined
0 0
0 0
0 unchanged
0x55 0x55
undefined unchanged
0 0
3 unchanged
0 unchanged
1 unchanged
0 unchanged
0 unchanged
7 unchanged
7 unchanged
undefined operates during reboot
undefined unchanged
undefined unchanged
0 unchanged
0 unchanged
0 unchanged
0 unchanged
0 unchanged
0 unchanged
0 unchanged
undefined unchanged
undefined unchanged
undefined unchanged
0 unchanged
0 unchanged
0 unchanged
0 unchanged
0 0
undefined unchanged
undefined unchanged
undefined unchanged