Alu Overflow Latch Mode; Division - Analog Devices adsp-2100 Manual

When the ALU saturation mode is used, only the AR register saturates; if
the AF register is the destination, wrap-around will occur but the flags
will reflect the saturated result.
2.2.6

ALU Overflow Latch Mode

The ALU overflow latch mode, enabled by setting bit 2 in the mode status
register (MSTAT), causes the AV bit to "stick" once it is set. In this mode,
when an ALU overflow occurs, AV will be set and remain set, even if
subsequent ALU operations do not generate overflows. In this mode, AV
can only be cleared by writing a zero to it directly from the DMD bus.
2.2.7

Division

The ALU supports division. The divide function is achieved with
additional shift circuitry not shown in Figure 2.2. Division is accomplished
with two special divide primitives. These are used to implement a non-
restoring conditional add-subtract division algorithm. The division can be
either signed or unsigned; however, the dividend and divisor must both
be of the same type. Appendix B details various exceptions to the normal
division operation as described in this section.
A single-precision divide, with a 32-bit dividend (numerator) and a 16-bit
divisor (denominator), yielding a 16-bit quotient, executes in 16 cycles.
Higher and lower precision quotients can also be calculated. The divisor
can be stored in AX0, AX1 or any of the R registers. The upper half of a
signed dividend can start in either AY1 or AF. The upper half of an
unsigned dividend must be in AF. The lower half of any dividend must be
in AY0. At the end of the divide operation, the quotient will be in AY0.
The first of the two primitive instructions "divide-sign" (DIVS) is executed
at the beginning of the division when dividing signed numbers. This
operation computes the sign bit of the quotient by performing an
exclusive-OR of the sign bits of the divisor and the dividend. The AY0
register is shifted one place so that the computed sign bit is moved into
the LSB position. The computed sign bit is also loaded into the AQ bit of
the arithmetic status register. The MSB of AY0 shifts into the LSB position
of AF, and the upper 15 bits of AF are loaded with the lower 15 R bits
from the ALU, which simply passes the Y input value straight through to
the R output. The net effect is to left shift the AF-AY0 register pair and
move the quotient sign bit into the LSB position. The operation of DIVS is
illustrated in Figure 2.3 (on the next page).
Computational Units 2
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