Analog Devices adsp-2100 Manual page 160

7 Host Interface Port
selects a multiplexed read/write select with data strobe, and HMD1
selects separate address and data buses. The timing for the read cycle and
the write cycle is as follows:
1. The host asserts HRW and the address.
2. The host asserts HDS and HSEL.
3. The ADSP-21xx returns HACK (and, for a read cycle, the data).
4. For a write cycle, the host asserts the data.
5. The host deasserts HDS and HSEL.
6. The host deasserts HRW and the address (and, for a write cycle, the
data).
7. The ADSP-21xx deasserts HACK (and, for a read cycle, the data).
Figure 7.8 shows the HIP timing when HMD0=0 and HMD1=1. HMD0
selects separate read and write strobes, and HMD1 selects multiplexed
address and data buses. HD0-HD2 are used for the address. The timing
HSEL
Host Write Cycle
HWR
HACK
HAD15–0
HSEL
Host Read Cycle
HRD
HACK
HAD15–0
Figure 7.8 HIP Timing: Separate Strobes, Multiplexed Buses
7 – 14
ALE
ADDRESS
ALE
ADDRESS
DATA
DATA