Word Length - Analog Devices adsp-2100 Manual

External serial clock frequencies may be as high as the processor's cycle
rate, up to a maximum of 13.824 MHz; internal clock frequencies may be
as high as one-half the processor's clock rate. The frequency of an
internally generated clock is a function of the processor clock frequency
(as seen at the CLKOUT pin) and the value of the 16-bit serial clock divide
modulus register SCLKDIV (0x3FF5 for SPORT0 and 0x3FF1 for SPORT1).
SCLK frequency = –––––––––––––––––—
Table 5.5 shows how some common SCLK frequencies correspond to
values of SCLKDIV.
SCLKDIV SCLK Frequency
20479 300 Hz
5119 1200 Hz
639 9600 Hz
95 64 kHz
3 1.536 MHz
2 2.048 MHz
0 6.144 MHz
(Assumes CLKOUT frequency of 12.288 MHz)
Table 5.5 Common Serial Clock Frequencies (Internally Generated)
If the value of SCLKDIV is changed while the internal serial clock is
enabled, the change in SCLK frequency takes effect at the start of the next
rising edge of SCLK.
Note that the serial clock of SPORT1 (the SCLK pin) still functions when
the port is being used in its alternate configuration (as FO, FI and two
interrupts). In this case, SCLK is unresponsive to an external clock, but can
internally generate a clock signal as described above.
5.6
Each SPORT independently handles words of 3 to 16 bits. The data is
right-justified in the SPORT data registers if it is fewer than 16 bits long.
The serial word length (SLEN) field in each SPORT control register
determines the word length according to this formula:
Serial Word Length = SLEN + 1
Serial Ports
CLKOUT frequency
2 x (SCLKDIV + 1)

WORD LENGTH

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