Analog Devices adsp-2100 Manual page 438

DREG Data Register codes
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
DV Divisor codes for Slow Idle instruction ( IDLE (n) )
0 0 0 0
0 0 0 1
0 0 1 0
0 1 0 0
1 0 0 0
FIC FI condition code
1
0
FO Control codes for Flag Output Pins (FO, FL0, FL1, FL2)
.
0 0
0 1
1 0
1 1
Instruction Coding
AX0
AX1
MX0
MX1
AY0
AY1
MY0
MY1
SI
SE
AR
MR0
MR1
MR2
SR0
SR1
Normal Idle instruction (Divisor=0)
Divisor=16
Divisor=32
Divisor=64
Divisor=128
latched FI is 1
latched FI is 0
No change
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" FLAG_IN "
" NOT FLAG_IN "
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