Boot Loading Through The Hip - Analog Devices adsp-2100 Manual

7 Host Interface Port
1. The host asserts ALE.
2. The host drives the address.
3. The host deasserts ALE.
4. The host stops driving the address.
5. The host asserts HRW.
6. The host asserts HDS and HSEL.
7. The ADSP-21xx returns HACK (and, for a read cycle, the data).
8. For a write cycle, the host asserts the data.
9. The host deasserts HDS and HSEL.
10. The host deasserts HRW (and, for a write cycle, the data).
11. The ADSP-21xx deasserts HACK (and, for a read cycle, the data).
7.7
THROUGH THE HIP
The entire internal program RAM of the ADSP-21xx, or any portion of it,
can be loaded using a boot sequence. Upon hardware or software reset,
the boot sequence occurs if the MMAP pin is 0. If the MMAP pin is 1, the
boot sequence does not occur.
The ADSP-21xx can boot in either of two ways: from external memory
(usually EPROM), through the boot memory interface, or from a host
processor, through the HIP. The BMODE pin selects which type of booting
occurs.
When BMODE=0, booting occurs through the memory interface. This
process is described in Chapter 10, "Memory Interface." When the
BMODE=1, booting occurs through the HIP.
To generate a file for HIP booting, use the HIP Splitter utility program of
the ADSP-2100 Family Development Software. (This utility produces HIP
boot files while the PROM Splitter utility produces files for EPROM
booting.)
The BMS signal is asserted when booting through the HIP just as when
booting through the memory interface; in this case, it serves as an
indication that the boot sequence is occurring. Boot memory wait states
have no effect when booting through the HIP.
Booting through the HIP occurs in the following sequence:
1. After reset, the host writes the length of the boot sequence to HDR3.
7 – 16
BOOT LOADING