Analog Devices adsp-2100 Manual page 14

1 Introduction
Feature
Arithmetic/Logic Unit
Multiply/Accumulator
Shifter
Data Address Generators
Program Sequencer
Data Memory RAM
Program Memory RAM
Timer
Serial Port 0
(Multichannel)
Serial Port 1
Host Interface Port
DMA Ports
Analog Interface
Supply Voltage
Instruction Rate
(MIPS)
Table 1.1 ADSP-2100 Family Processor Features & On-Chip Peripherals
• Memory—The ADSP-2100 family uses a modified Harvard architecture
in which data memory stores data, and program memory stores both
instructions and data. All ADSP-2100 family processors contain on-
chip RAM that comprises a portion of the program memory space and
data memory space. The speed of the on-chip memory allows the
processor to fetch two operands (one from data memory and one from
program memory) and an instruction (from program memory) in a
single cycle.
• Serial Ports—The serial ports (SPORTs) provide a complete serial
interface with hardware companding for data compression and
expansion. Both µ-law and A-law companding are supported. The
SPORTs interface easily and directly to a wide variety of popular serial
devices. Each SPORT can generate a programmable internal clock or
accept an external clock. SPORT0 includes a multichannel option.
• Timer—A programmable timer/counter with 8-bit prescaler provides
periodic interrupt generation.
• Host Interface Port—The Host Interface Port (HIP) allows direct
connection (with no glue logic) to a host processor. The HIP is made up
of 16 data pins and 11 control pins. The HIP is extremely flexible and
has provisions to allow simple interface to a variety of host processors.
For example, the Motorola 68000, the Intel 8051, or another ADSP-2100
family processor can be easily connected to the HIP.
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2101 2103 2105
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2115 2111 2171
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2173 2181 2183 21msp58
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3.3V 5V 3.3V
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5V
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