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COMPUTATION with REGISTER to REGISTER MOVE
results in an assembler warning, but assembles and executes exactly as the
first form of the instruction. Note that reading example (2) from left to
right may suggest that the MR1 register value is loaded into AX0 and then
AX0 is used in the computation, all in the same cycle. In fact, this is not
possible. The left-to-right logic of example (1) suggests the operation of
the instruction more closely. Regardless of the apparent logic of reading
the instruction from left to right, the read-first, write-second operation of
the processor determines what actually happens.
Using the same register as a destination in both clauses, however,
produces an indeterminate result and should not be done. The assembler
issues a warning unless semantics checking is turned off. Regardless of
whether or not the warning is produced, however, this practice is not
supported.
The following, therefore, is illegal and not supported, even though
assembler semantics checking produces only a warning:
(3) AR = AX0 + AY0, AR = MR1;
Status Generated:
single function versions of the selected arithmetic operation.
<ALU> operation
ASTAT:
7
6
SS MV AQ AS
-
-
AZ
Set if result equals zero. Cleared otherwise.
AN
Set if result is negative. Cleared otherwise.
AV
Set if an overflow is generated. Cleared otherwise.
AC
Set if a carry is generated. Cleared otherwise.
AS
Affected only when executing the Absolute Value operation
(ABS). Set if the source operand is negative.
All status bits are affected in the same way as for the
5
4
3
AC AV AN AZ
-
*
*
(instruction continues on next page)
MULTIFUNCTION
Illegal!
2
1
0
*
*
*
15
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