Table of Contents
Advertisement
Memory-Mapped Registers
XTAL Pin Disable During Powerdown
1=disabled, 0=enabled
(XTAL pin should be disabled when
no external crystal is connected)
XTALDELAY
Delay Startup From Powerdown 4096 Cycles
1=delay, 0=no delay
(use delay to allow internal phase locked
loop or external oscillator to stabilize)
Powerdown Force
1=force processor to vector to
powerdown interrupt
Powerup Context Reset
1=soft reset (clear context)
0=resume execution
XTAL Pin Disable During Powerdown
1=disabled, 0=enabled
(XTAL pin should be disabled when
no external crystal is connected)
Delay Startup From Powerdown 4096 Cycles
1=delay, 0=no delay
Powerdown Force
1=force processor to vector to
powerdown interrupt
Powerup Context Reset
1=soft reset, 0=resume execution
Default bit values at reset are shown; if no value is shown, the bit is undefined at reset.
Reserved bits are shown on a gray field—these bits should always be written with zeros.
Control/Status Registers
SPORT1 Autobuffer Control Register
15
14
13
0
0
0
XTALDIS
PDFORCE
PUCR
XTALDIS, XTALDELAY, PDFORCE, and PUCR are only on the
ADSP-2171, ADSP-2181, and ADSP-21msp58/59 processors.
Analog Autobuffer Control Register
15
14
13
0
0
0
XTALDIS
XTALDELAY
PDFORCE
PUCR
12
11
10
9
8
7
0
12
11
10
9
8
7
0
(Not on ADSP-21msp5x)
6
5
4
3
2
1
0
0
6
5
4
3
2
1
0
0
0
E
0
DM(0x3FEF)
RBUF
Receive Autobuffer Enable
TBUF
Transmit Autobuffer Enable
RMREG
Receive M register
RIREG
Receive I register
TMREG
Transmit M register
TIREG
Transmit I register
(ADSP-21msp5x only)
DM(0x3FEF)
ARBUF
ADC Receive Autobuffer Enable
ATBUF
DAC Transmit Autobuffer Enable
ARMREG
Receive M register
ARIREG
Receive I register
ATMREG
Transmit M register
ATIREG
Transmit I register
E – 7
- Quick Links:
- Overview
Hide quick links:
Advertisement
Table of Contents
