Exiting Powerdown; Pwd Pin - Analog Devices adsp-2100 Manual

9 System Interface
9.7.3

Exiting Powerdown

The powerdown mode can be exited with the use of the PWD pin or with
RESET. There are also several user-selectable modes for start-up from
powerdown which specify a start-up delay as well as specify the program
flow after start-up. This allows the program to resume from where it left
off before powerdown or for the program context to be cleared.
9.7.3.1 Ending Powerdown With The PWD Pin
Applying a low-to-high transition to the PWD pin will take the processor
out of powerdown mode. You have the option of selecting the amount of
time the processor takes to come out of the powerdown mode with the
"delay start-up from powerdown" control bit (XTALDELAY, bit 14 in the
Powerdown Control Register.) If this bit is cleared to 0, no additional
delay over the quick start-up (100 cycles) is introduced. If this bit is set to
1, a delay of 4096 cycles is introduced. The delay feature is used
depending upon the state of an external clock oscillator at the time of
powerup or if the internal clock is disabled. This is further discussed in the
sections "Systems Using an External TTL/CMOS Clock" and "Systems
Using a Crystal and The Internal Oscillator."
You can also program one of two options directing the processor how to
resume operation. The context for exiting powerdown is set by bit 12
(PUCR, powerup context reset) of the Powerdown Control Register.
If the PUCR control bit is cleared to 0, the processor will continue to
execute instructions following the IDLE instruction. For example, a high-
to-low transition is applied to the PWD pin which causes the processor to
vector to the powerdown interrupt routine. In this routine, a few
housekeeping tasks are performed and the IDLE instruction is executed.
The processor powers down. Some time later a low-to-high transition is
applied to the PWD pin, causing the processor to exit powerdown mode.
Since the PUCR bit is 0, the processor resumes executing instructions in
the powerdown interrupt routine, starting at the instruction following the
IDLE instruction. When an RTI instruction is encountered, control then
passes back to the main routine.
If the PUCR bit is set to 1 for a clear context, the processor resumes
operation from powerdown by clearing the PC, STATUS, LOOP and
CNTR stacks. The IMASK and ASTAT registers are set to 0 and the SSTAT
goes to 0x55. The processor will start executing instructions from address
0x0000.
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