Boot Loading Through The Idma Port - Analog Devices adsp-2100 Manual

11 DMA Ports
Note: IDMA port writes to Program Memory require two IDMA port
write cycles to write a word to ADSP-2181 internal Program Memory. The
ADSP-2181 acknowledges the IDMA port write of the first 16 bits (MSBs
of PM word) as they are written to a temporary holding latch, not waiting
for an instruction cycle boundary. The ADSP-2181 does not assert the
IACK
writes) until the internal memory write is complete and the IDMA port is
ready for another transaction.
Warning: If an IDMA address latch cycle or a ADSP-2181 write to the
IDMA Control register occur after a first Program Memory write cycle, the
IDMA port will lose the first half of the Program Memory word. The next
Program Memory write will be considered the first half of a Program
Memory write pair.
There are two features that differentiate between the IDMA Port long
write and short write. The long write supports hosts (processors or ASICs)
that allow a data-written acknowledge. If your host needs the ADSP-2181
to signal that it has written the data, use the IDMA long read cycle.
The short write lets your host hold data on the bus just until it is latched
and then release the bus. If you are using the ADSP-2181 in a
multiprocessing environment, using the short write is one way to avoid
tying up the IAD15-0 data bus (waiting for
also useful for hosts that can handle the short write timing, but can't
extend the accesses with
11.3.5
The ADSP-2181 supports boot loading through the IDMA port. To boot
through the IDMA Port, use the following steps:
• Reset the processor (assert
• Set MMAP=0 and BMODE=1. These pin settings select IDMA booting.
• Deassert
• Load ADSP-2181 internal memory through the IDMA port. Program
execution is held off until you write to Program Memory address zero,
PM(0x0000). The ADSP-2181 responds to IDMA control signals (IAL,
IS
,
manner as during non-booting IDMA transfers.
• Write to PM(0x0000) to begin program execution.
Warning: Make certain to load all of the necessary memory locations with
the proper data before writing to PM(0x0000).
11 – 24
line after the second Program Memory write (or all Data Memory

Boot Loading Through The IDMA Port

RESET
.
IWR IRD
, and ) and provides acknowledge (
IACK
IACK
(when holdoffs occur).
RESET
).
signal). Short writes are
IACK
) in the same