Computation With Data Register Move - Analog Devices adsp-2100 Manual

Adsp-2100 family programmable single-chip microprocessors
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Instruction Set Reference
that the result of the computation is written to memory when, in fact, the
previous value of the register is what is written. There is no requirement
that the same register be used in this way although this will usually be the
case in order to pipeline operands to the computation.
The restrictions on computation operations are identical to those given
above. All ALU operations except division, all MAC operations, and all
Shifter operations except SHIFT IMMEDIATE are legal. Computations
must be unconditional.
15.4.5

Computation With Data Register Move

This final type of multifunction instruction performs a data register to
data register move in parallel with a computation. Most of the restrictions
applying to the previous two instructions also apply to this instruction.
AR=AX0+AY0, AX0=MR2;
Here an ALU addition operation occurs while a new value is loaded into
AX0 from MR2. As before, the value of AX0 at the beginning of the
instruction is the value used in the computation. The move may be from
or to all ALU, MAC and Shifter input and output registers except the
feedback registers (AF and MF) and SB.
In the example, the data register move loads the AX0 register with the
new value at the end of the cycle. All ALU operations except division, all
MAC operations and all Shifter operations except SHIFT IMMEDIATE are
legal. Computation must be unconditional.
A complete list of data registers is given in Table 15.7. A complete list of
the permissible xops and yops for computational operations is given in the
reference page for each instruction. Table 15.1 shows the legal
combinations for multifunction instructions: you may combine operations
on the same row with each other.
Unconditional Computations
None or any ALU (except Division) or MAC
Any ALU except Division
Any MAC
Any Shift except Immediate
Table 15.1 Summary Of Valid Combinations For Multifunction Instructions
Data Move
(DM=DAG1)
DM read
{ }
DM read
DM write
Register-To-Register
15
Data Move
(PM=DAG2)
PM read
PM read
PM write
15 – 7

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