Analog Autobuffer/Powerdown Register - Analog Devices adsp-2100 Manual

8 Analog Interface
15 14 13
0 0
ADC Offset
IG0
ADC Input Gain (ADC PGA)
DABY
DAC High Pass Filter Bypass
1=bypass, 0=insert
ADBY
ADC High Pass Filter Bypass
1=bypass, 0=insert
Figure 8.4 Analog Control Register

8.4.1.2 Analog Autobuffer/Powerdown Register

The analog autobuffer/powerdown register (located at address 0x3FEF
in data memory) is shown in Figure 8.5. This register enables or
disables autobuffering of ADC receive data and/or DAC transmit
data—autobuffering is enabled by writing ones to the ARBUF (bit 0)
and/or ATBUF (bit 1) bits. When autobuffering is enabled, I (index)
and M (modify) registers are selected in bits 2–11 for the receive
and/or transmit data buffers. See "Autobuffering" in the Serial Ports
chapter for details on autobuffering.
8 – 10
Analog Control Register
12 11 10 9
0 0 0 0 0
All bits are set to 0 at processor reset.
(Reserved bits 10-15 must always be set to 0.)
IG1, IG0
ADC Input Gain (ADC PGA)
Gain IG1 IG0
0 dB 0 0
+6 dB 0 1
+20 dB 1 0
+26 dB 1 1
8 7 6 5 4
0 0 0 0 0
OG2 OG1
OG2, OG1, OG0
DAC Output Gain (DAC PGA)
Gain
+6 dB
+3 dB
0 dB
–3 dB
–6 dB
–9 dB
–12 dB
–15 dB
3 2 1 0
0 0 0 0
DM(0x3FEE)
DM[0x3FEE]
OG0
IG1
ADC Input Gain (ADC PGA)
IMS
ADC Input Multiplexer Select
1=AUX input, 0=NORM input
OG2, OG1, OG0
DAC Output Gain (DAC PGA)
APWD
Analog Interface Powerdown
0=powerdown, 1=enable
(Set both bits to 1 to
enable analog interface)
OG2 OG1 OG0
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1