Analog Devices adsp-2100 Manual page 225

10 Memory Interface
As shown in Figure 10.11, the ADSP-2101, ADSP-2111, ADSP-2105,
ADSP-2115, and ADSP-2161/62/63/64 processors have five external wait
state zones (DWAIT0–DWAIT4). Each of the five zones of external data
memory has its own programmable number of wait states. Wait states are
extra cycles that the processor either waits before latching data (on a read)
or drives the data (on a write). This means that one zone of memory could
be used for working with memory-mapped peripherals of one speed
while another zone was used with faster or slower peripherals. Similarly,
slower and faster memories can be used for different purposes, as long as
they are located in different zones of the data memory map.
As shown in Figures 10.12 and 10.13, the ADSP-2171, ADSP-21msp58/59,
and ADSP-2165/66 processors each have three wait state zones for
external data memory.
12K External
2K Internal
Data RAM
1K Reserved
Memory Mapped
Registers/Reserved
Data Memory
Figure 10.12 Data Memory Map (ADSP-2171, ADSP-21msp58/59)
10 – 12
0000
2FFF
3000
37FF
3800
3BFF
3C00
3FFF
0000
DWAIT 0
(1K External)
03FF
0400
DWAIT 1
(1K External)
07FF
0800
DWAIT 2
(10K External)
2FFF
3000
No Wait States
3FFF
Wait States