Transmit Interrupt Timing - Analog Devices adsp-2100 Manual

5 Serial Ports
when the data value was loaded into the transmit register.
(Note that if the transmit frame sync is generated externally, data starts
transmitting when a frame sync signal is received.)
After the TX register is loaded, it takes three complete phases of the serial
clock, HIGH, LOW and HIGH, in that order, to ensure synchronization
(see Figure 5.30). Once synchronization has been ensured and a frame
sync generated, the most significant bit of the transmit word is shifted out
on the same rising edge as the frame sync if alternate framing is used and
on the rising edge of the next serial clock if normal framing is used.
Therefore, the worst-case synchronization delay is two SCLK cycles.
There is additional delay if the previous data transmission has not
TFS
DT
SCLK
Interrupt or Autobuffer Request
Figure 5.31 SPORT Interrupt or Autobuffer Timing, Transmit 4-Bit Words (No Companding)
completed; the TX register cannot be loaded into the transmit shift register
until the previous transmission is complete.

5.13.4 Transmit Interrupt Timing

Once the MSB has been transmitted, the subsequent bits are transmitted
on the rising edges of the SCLK. The transmit interrupt (or autobuffer
request) is generated internally on the falling edge of SCLK during the
transmission of the second bit (see Figure 5.31 below). This timing gives
the program time to load the TX register with the next data for continuous
data transmission.
The transmit interrupt, like any other interrupt, must be synchronized to
the processor clock. Servicing is subject to the same latencies as other
interrupts.
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BIT3 BIT2 BIT1 BIT0