Analog Devices adsp-2100 Manual page 3

3.5 STATUS REGISTERS & STATUS STACK .................................... 3-20
3.5.1 Arithmetic Status Register (ASTAT) ....................................... 3-20
3.5.2 Stack Status Register (SSTAT) .................................................. 3-21
3.5.3 Mode Status Register (MSTAT) ............................................... 3-22
3.6 CONDITIONAL INSTRUCTIONS ............................................... 3-24
3.7 TOPPCSTACK ................................................................................. 3-25
3.7.1 TOPPCSTACK Restrictions ...................................................... 3-27
CHAPTER 4
4.1 OVERVIEW ........................................................................................ 4-1
4.2 DATA ADDRESS GENERATORS (DAGS) ................................... 4-1
4.2.1 DAG Registers .............................................................................. 4-1
4.2.2 Indirect Addressing ..................................................................... 4-3
4.2.2.1 Initialize L Registers To 0 For Non-Circular Addressing 4-3
4.2.3 Modulo Addressing (Circular Buffers)..................................... 4-4
4.2.4 Calculating The Base Address ................................................... 4-5
4.2.4.1 Circular Buffer Base Address Example 1 ........................... 4-5
4.2.4.2 Circular Buffer Base Address Example 2 ........................... 4-5
4.2.4.3 Circular Buffer Operation Example 1 ................................. 4-5
4.2.4.4 Circular Buffer Operation Example 2 ................................. 4-6
4.2.5 Bit-Reverse Addressing .............................................................. 4-6
4.3 PROGRAMMNG DATA ACCESSES ............................................. 4-7
4.3.1 Variables & Arrays ...................................................................... 4-7
4.3.2 Circular Buffers ............................................................................ 4-8
4.4 PMD-DMD BUS EXCHANGE ......................................................... 4-9
4.4.1 PMD-DMD Block Diagram Discussion .................................... 4-9
CHAPTER 5
5.1 OVERVIEW ........................................................................................ 5-1
5.2 BASIC SPORT DESCRIPTION ........................................................ 5-1
5.2.1 Interrupts ...................................................................................... 5-4
5.2.2 SPORT Operation ........................................................................ 5-4
5.3 SPORT PROGRAMMING ................................................................ 5-4
5.3.1 SPORT Configuration ................................................................. 5-5
5.3.2 Receiving And Transmitting Data ............................................ 5-6
5.4 SPORT ENABLE ................................................................................ 5-7
5.5 SERIAL CLOCKS ............................................................................... 5-8
5.6 WORD LENGTH ............................................................................... 5-9
5.7 WORD FRAMING OPTIONS ........................................................ 5-10
5.7.1 Frame Synchronization ............................................................. 5-10
5.7.2 Frame Sync Signal Source......................................................... 5-11
5.7.3 Normal And Alternate Framing Modes ................................. 5-13
5.7.4 Active High Or Active Low ..................................................... 5-14
DATA TRANSFER
SERIAL PORTS
Contents
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