Analog Devices adsp-2100 Manual page 462

E Control/Status Registers
Processor Core
DATA ADDRESS GENERATORS
DAG1
(DM addressing only)
Bit-reverse capability
I0 L0 M0
I1 L1 M1
I2 L2 M2
I3 L3 M3
14 14 14
PROGRAM SEQUENCER
18 5
LOOP ICNTL
STACK
4 X 18
IFC*
14
OWRCNTR
CNTR
IMASK*
COUNT
STACK
STATUS STACK*
4 X 14
* Width and depth vary with processor
ALU
AX0 AX1 AY0 AY1
AR AF
SHIFTER
8 5
SI SE SB
SR1 SR0
HOST INTERFACE PORT
(ADSP-2171, ADSP-2111, ADSP-21msp5x)
0x3FE8
HMASK
0x3FE5
Status Registers
0x3FE4
0x3FE7 HSR7
0x3FE3
0x3FE6
HSR6
0x3FE2
0x3FE1
0x3FE0
E – 2
DAG2
(DM and PM addressing)
Indirect branch capability
I4 L4 M4
I5 L5 M5
I6 L6 M6
I7 L7 M7
14 14 14
14
PC
STACK
16 X 14
8
SSTAT
8
MSTAT* ASTAT
MAC
MX0 MX1 MY0 MY1
8 16 16
MR2 MR1 MR0 MF
BUS EXCHANGE
8
PX
Data Registers
HDR5
HDR4
HDR3
HDR2
HDR1
HDR0
TIMER
0x3FFD TPERIOD
0x3FFC TCOUNT
0x3FFB TSCALE
SPORT 0
RX0
Multichannel enables
0x3FFA
RX 31-16
0x3FF9 RX 15-0
0x3FF8 TX 31-16
0x3FF7 TX 15-0
SPORT0 Control
0x3FF6 Control
0x3FF5 SCLKDIV
0x3FF4
0x3FF3 Autobuffer
SPORT 1
RX1
SPORT1 Control
0x3FF2
0x3FF1
0x3FF0
0x3FEF
IDMA PORT
BDMA PORT
PROGRAMMABLE FLAGS
(ADSP-2181)
IDMA Registers
IDMA Control
0x3FE0
Register
Programmable
Flag Registers
PFTYPE
0x3FE6
0x3FE5 PFDATA
MEMORY INTERFACE
0x3FFF
0x3FFE
3
TX0
ANALOG INTERFACE
RFSDIV
0x3FEF
0x3FEE
0x3FED
0x3FEC
TX1
Control
SCLKDIV
RFSDIV
Autobuffer
BDMA Registers
0x3FE4
BWCOUNT
0x3FE3 BDMA Control
0x3FE2
BEAD
0x3FE1
BIAD
System Control
Register
Wait States
(ADSP-2181)
3
DMOVLAY PMOVLAY
(ADSP-21msp5x)
Autobuffer
Control
ADC Receive
DAC Transmit