Analog Devices adsp-2100 Manual page 48

2 Computational Units
The shifter contains a duplicate bank of registers, shown in Figure 2.9
behind the primary registers. There are actually two sets of SE, SB, SI, SR1,
and SR0 registers. Only one bank is accessible at a time. The additional
bank of registers can be activated for extremely fast context switching. A
new task, such as an interrupt service routine, can then be executed
without transferring current states to storage.
The selection of the primary or alternate bank of registers is controlled by
bit 0 in the processor mode status register (MSTAT). If this bit is a 0, the
primary bank is selected; if it is a 1, the secondary bank is selected.
The shifting of the input is determined by a control code (C) and a HI/LO
reference signal. The control code is an 8-bit signed value which indicates
the direction and number of places the input is to be shifted. Positive
codes indicate a left shift (upshift) and negative codes indicate a right shift
(downshift). The control code can come from three sources: the content of
the shifter exponent (SE) register, the negated content of the SE register or
an immediate value from the instruction.
The HI/LO signal determines the reference point for the shifting. In the HI
state, all shifts are referenced to SR1 (the upper half of the output field),
and in the LO state, all shifts are referenced to SR0 (the lower half). The
HI/LO reference feature is useful when shifting 32-bit values since it
allows both halves of the number to be shifted with the same control code.
HI/LO reference signal is selectable each time the shifter is used.
The shifter fills any bits to the right of the input value in the output field
with zeros, and bits to the left are filled with the extension bit (X). The
extension bit can be fed by three possible sources depending on the
instruction being performed. The three sources are the MSB of the input,
the AC bit from the arithmetic status register (ASTAT) or a zero.
Table 2.4 shows the shifter array output as a function of the control code
and HI/LO signal.
The OR/PASS logic allows the shifted sections of a multiprecision number
to be combined into a single quantity. In some shifter instructions, the
shifted output may be logically ORed with the contents of the SR register;
the shifter array is bitwise ORed with the current contents of the SR
register before being loaded there. When the [SR OR] option is not used in
the instruction, the shifter array output is passed through and loaded into
the shifter result (SR) register unmodified.
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