Analog Devices adsp-2100 Manual page 464

Adsp-2100 family programmable single-chip microprocessors
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E Control/Status Registers
Memory-Mapped Registers
Multichannel Enable
Internal Serial Clock Generation
Receive Frame Sync Required
Receive Frame Sync Width
Multichannel Frame Delay
(Only If Multichannel Mode Enabled )
Transmit Frame Sync Required
Transmit Frame Sync Width
Internal Transmit Frame Sync Enable
(or MCL Multichannel Length:
1=32 words, 0=24 words)
(Only If Multichannel Mode Enabled )
Receive
Word
Enables
Transmit
Word
Enables
E – 4
SPORT0 Control Register
15
14
13
12
11
0
0
0
0
0
MCE
ISCLK
RFSR
RFSW
MFD
TFSR
TFSW
ITFS
SPORT0 Multichannel Word Enables
31
30
29
28
27
15
14
13
12
11
31
30
29
28
27
15
14
13
12
11
10
9
8
7
6
5
0
0
0
0
0
0
26
25
24
23
22
21
10
9
8
7
6
5
26
25
24
23
22
21
10
9
8
7
6
5
1 = channel enabled
0 = channel ignored
(Not on ADSP-2105)
4
3
2
1
0
0
0
0
0
0
DM(0x3FF6)
SLEN (Serial Word Length – 1)
DTYPE Data Format
00=right justify, zero-fill unused MSBs
01=right justify, sign-extend into unused MSBs
10=compand using µ-law
11=compand using A-law
INVRFS
Invert Receive Frame Sync
INVTFS
Invert Transmit Frame Sync
(or INVTDV Invert Transmit Data Valid)
(Only If Multichannel Mode Enabled )
IRFS
Internal Receive Frame Sync Enable
(Not on ADSP-2105)
R
W
20
19
18
17
16
E
DM(0x3FFA)
0
4
3
2
1
0
DM(0x3FF9)
0
20
19
18
17
16
DM(0x3FF8)
0
4
3
2
1
0
DM(0x3FF7)
0

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