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10 Memory Interface
15
14
0
1
Figure 10.14 Data Memory Waitstate Control Register (ADSP-2101, ADSP-2111,
15
14
0
0
ROM Enable (ADSP-2172, ADSP-21msp59 only)
Figure 10.15 Data Memory Waitstate Control Register (ADSP-2171/72, ADSP-21msp58/59)
10.3.3
Peripherals requiring parallel communications and other types of devices
can be mapped into external data memory. Communication takes the form
of reading and writing the memory locations associated with the device.
Some A/D and D/A converters require this type of interface. The .PORT
directives in the System Builder and Assembler modules of the ADSP-2100
Family Development Software support this mapping.
Communication with a memory-mapped device consists simply of reading
and writing the appropriate locations. By matching the access times of the
external devices to the wait states specified for their zone of data memory,
you can easily interface a variety of devices.
The 16 MSBs of the external data bus (D
the internal DMD bus, so D
10 – 14
13
12
11
10
1
1
1
1
DWAIT4
DWAIT3
ADSP-2105, ADSP-2115, ADSP-2161/62/63/64)
13
12
11
10
0
0
0
0
1=enable
0=disable
Memory-Mapped Peripherals
9
8
7
6
5
1
1
1
1
1
DWAIT2
DWAIT1
9
8
7
6
5
0
1
1
1
1
DWAIT2
DWAIT1
) are connected to the 16 LSBs of
23-8
should be used for 16-bit peripherals.
23-8
4
3
2
1
0
1
1
1
1
1
DWAIT0
4
3
2
1
0
1
1
1
1
1
DWAIT0
DM(0x3FFE)
DM(0x3FFE)
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