Example Program: Setup Routine Discussion - Analog Devices adsp-2100 Manual

12 Programming Model
.CONST taps=15, taps_less_one=14;
Listing 12.1 (cont.) Include File, Constants Initialization
12.2.1

Example Program: Setup Routine Discussion

The setup and main loop routine performs initialization and then loops on
the IDLE instruction to wait until the receive interrupt from SPORT0
occurs. The filter is interrupt-driven. When the interrupt occurs control
shifts to the interrupt service routine (shown in Listing 12.2).
Line A of the program shows that the constant declarations are contained
in a separate file.
Section B of the program includes the assembler directives defining two
circular buffers in on-chip memory: one in data memory RAM (used to
hold a delay line of samples) and one in program memory RAM (used to
store coefficients for the filter). The coefficients are actually loaded from
an external file by the linker. These values can be changed without
reassembling; only another linking is required.
Section C shows the setup of interrupts. Since this code module is located
at absolute address zero (as indicated by the ABS qualifier in the
.MODULE directive), the first instruction is placed at the restart vector:
address 0x0000. The first location is the restart vector instruction, which
jumps to the routine restarter. Interrupt vectors that are not used are filled
with a return from interrupt instruction followed by NOPs. (Since only
one interrupt will be enabled, this is only a thorough programming
practice rather than a necessity.) The SPORT0 receive interrupt vector
jumps to the interrupt service routine.
Section D, restarter, sets up the index (I), length (L), and modify (M)
registers used to address the two circular buffers. A non-zero value for
length activates the processor's modulus logic. Each time the interrupt
occurs, the I register pointers advance one position through the buffers.
The clear loop zeroes all values in the data memory buffer.
Section E, after clear, sets up the processor's memory-mapped control
registers used in this system. See Appendix E for control register
initialization information.
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