Analog Devices adsp-2100 Manual page 83

MSTAT can be modified by writing a new value to it with a MOVE
instruction. Unlike the other status registers, MSTAT can also be altered
with the Mode Control instruction (ENA, DIS). The Mode Control
instruction provides a high-level, self-documenting method of configuring
the processors' operating modes. Refer to the description of the Mode
Control instruction in Chapter 15, "Instruction Set Reference," for further
details.
To enable the bit reverse mode, for example, the following instruction
could be used:
ENA BIT_REV;
The bit-reverse mode, when enabled, bitwise reverses all addresses
generated by data address generator 1 (DAG1). This is useful for
reordering the input or output data of an FFT algorithm.
The ADSP-2100 family processors include a secondary register set which
can be used to provide a fresh set of ALU, MAC, and Shifter registers at
any time, for example during execution of a subroutine. The data register
bank select bit of MSTAT determines which set of data registers is active
(0=primary, 1=secondary). The secondary register set duplicates all of the
input and result registers of the computation units, ALU, MAC, and
Shifter:
AX0 MX0 SI
AX1 MX1 SE
AY0 MY0 SB
AY1 MY1 SR1
AF MF SR0
AR MR0
MR1
MR2
The following mode control instruction, for example, switches from the
processor's primary register set to its secondary register set:
ENA SEC_REG;
while the following instruction switches back to the primary register set:
DIS SEC_REG;
Program Control 3
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