Analog Devices adsp-2100 Manual page 111

5 Serial Ports
on its frame sync pin (RFS or TFS). If the IRFS or ITFS bit is a 1, the
processor generates its own frame sync signal and drives the RFS or TFS
pin as an output.
The IRFS bit is bit 8 in the SPORT control register (0x3FF6 for SPORT0 and
0x3FF2 for SPORT1), and the ITFS bit is bit 9. Both of these bits are cleared
at reset, that is, both serial ports require externally generated frame sync
signals for both transmitting and receiving data.
If frame sync signals are generated externally, then RFS and TFS are
inputs, and the external source controls data transmission and reception.
The SPORT will wait for a transmit frame sync before transmitting data
and for a receive frame sync before receiving data. If frame sync signals
are generated internally, however, then RFS and TFS are outputs, and the
processor controls the timing of data operations.
The SPORT outputs an internally generated transmit framing signal after
data is loaded into the transmit (TX0 or TX1) register, at the time needed
to ensure continuous data transmission, after the last bit of the current
word is transmitted (the exact time depends on the framing mode being
used; see "Normal and Alternate Framing Modes," the next section). The
occurrence of the transmit frame sync is a result of the availability of data
in the transmit register.
With an internally generated receive framing signal, the processor controls
the timing of the receive data. The external data source must provide data
to the serial port synchronized to the receive framing signal (the timing
depends on the framing mode being used; see "Normal and Alternate
Framing Modes," the next section). The processor generates RFS
periodically on a multiple of SCLK cycles, based on the value of the 16-bit
receive frame sync divide modulus register, RFSDIV (0x3FF4 for SPORT0
and 0x3FF0 for SPORT1):
Number of SCLK cycles between RFS assertions = RFSDIV + 1
For example, to allow 256 SCLK cycles between RFS assertions, set
RFSDIV to 255 (0xFF).
Values of RFSDIV+1 that are less than the word length are not
recommended.
Note that frame sync signals may be generated internally even when
5 – 12