Bus Request/Grant - Analog Devices adsp-2100 Manual

10.5 BUS REQUEST / GRANT
This section describes the bus request and grant feature of all ADSP-21xx
processors, including the ADSP-2181.
The ADSP-21xx can relinquish control of its data and address buses to an
external device. The external device requests the bus by asserting (low) the
bus request signal,
performing an external access, it responds to the active
following processor cycle by:
• tristating the data and address buses and the
• asserting the bus grant (
• halting program execution (unless Go Mode is enabled).
If Go Mode is enabled, the ADSP-21xx continues to execute instructions from
its internal memory. It will not halt program execution until it encounters an
instruction that requires an external access. (An "external access" may be
either a memory device access or, on the ADSP-2181, a memory overlay
access, BDMA access, or I/O space access.)
If Go Mode is not enabled, the ADSP-21xx always halts before granting the
bus. The processor's internal state is not affected by granting the bus, and the
serial ports and host interface port (on the ADSP-2111, ADSP-2171,
ADSP-21msp5x) remain active during a bus grant, whether or not the
processor core halts.
If the ADSP-21xx is performing an external access when the
asserted, it will not grant the buses until the cycle after the access completes.
The sequence of events is illustrated in Figure 10.21. The entire instruction
does not need to be completed when the bus is granted. If a single instruction
requires two external accesses, the bus will be granted between the two
accesses. The second access is performed after
BR
When the input is released, the ADSP-21xx releases the
reenables the output drivers and continues program execution from the point
BG
where it stopped.
BR
of is recognized. Refer to the data sheet for exact timing relationships.
The bus request feature operates at all times, including when the processor is
booting and when
BR
cycle that is recognized. During booting, the bus is granted after
completion of loading of the current byte (including any wait states). Using
bus request during booting is one way to bring the booting operation under
control of a host computer.
Memory Interface
BR BR
. is an asynchronous input. If the ADSP-21xx is not
BG
) signal, and
is always deasserted in the same cycle that the removal
RESET
is active. During
BR
input in the
xMS RD WR
, , output drivers,
BR
BR
is removed.
BG
RESET BG
, is asserted in the same
10
signal is
signal,
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