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The program memory interface can generate 0 to 7 wait states for external
memory devices. The program memory wait state field (PWAIT) in the
system control register is shown in Figure 10.3. PWAIT defaults (after
RESET
) to seven wait states for program memory accesses.
15
14
13
12
11
Figure 10.3 Program Memory Wait State Field In System Control Register
10.2.2 Program Memory Maps
For all RAM-based processors except the ADSP-2181, the program
memory space is mapped in one of two configurations depending on the
state of the MMAP pin. Figure 10.4 shows these configurations for the
processors with 2K internal program memory (ADSP-2101, ADSP-2111,
ADSP-2171, ADSP-21msp58), and Figure 10.5 shows the same information
for the processors with 1K internal program memory (ADSP-2105,
ADSP-2115).
When MMAP=0, internal RAM occupies 2K words beginning at address
0x0000. In this configuration, the boot loading sequence is automatically
RESET
initiated when
Interface").
When MMAP=1, words of external program memory begin at address
0x0000 and internal RAM is located in the upper 2K words, beginning at
address 0x3800. In this configuration, program memory is not loaded
although it can be written to and read from under program control.
The program memory space can hold instructions and data intermixed in
any combination. The ADSP-21xx linker determines where to place
relocatable code and data segments. You may specify absolute address
placement for any module or data structure, including the code for the
restart and interrupt vector locations. The restart vector is at program
memory address 0x0000. The interrupt vector locations are given in
Chapter 3 and in Appendix D.
Memory Interface
System Control Register
0x3FFF
10
9
8
7
6
(Program Memory Wait States)
is released (as described in "Boot Memory
5
4
3
2
1
0
PWAIT
Default = 7
10
10 – 5
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