Analog Devices adsp-2100 Manual page 66

Adsp-2100 family programmable single-chip microprocessors
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3
Program Control
The loop stack stores the last instruction addresses and termination
conditions of temporarily dormant loops. Up to four levels can be stored.
The only extra cycle associated with the nesting of DO UNTIL loops is the
execution of the DO UNTIL instruction itself, since the pushing and
popping of all stacks associated with the looping hardware is automatic.
When using the counter expired (CE) status as the termination condition
for the loop, an additional cycle is required for the initial loading of the
counter. Table 3.1 shows the termination conditions that can be used with
DO UNTIL.
Syntax
EQ
NE
LT
GE
LE
GT
AC
NOT AC
AV
NOT AV
MV
NOT MV
NEG
POS
CE
FOREVER
Table 3.1 DO UNTIL Termination Condition Logic
When a DO UNTIL instruction is executed, the 14-bit address of the last
instruction and a 4-bit termination condition (both contained in the DO
UNTIL instruction) are pushed onto the 18-bit by 4-word loop stack.
Simultaneously, the PC incrementer output is pushed onto the PC stack.
Since the DO UNTIL instruction is located just before the first instruction
of the loop, the PC stack then contains the first loop instruction address,
and the loop stack contains the last loop instruction address and
termination condition. The non-empty state of the loop stack activates the
loop comparator which compares the address on top of the loop stack
with the address of the next instruction. When these two addresses are
equal, the loop comparator notifies the next address source selector that
the last instruction in the loop will be executed on the next cycle.
3 – 6
Status Condition
Equal Zero
Not Equal Zero
Less Than Zero
Greater Than or Equal Zero
Less Than or Equal Zero
Greater Than Zero
ALU Carry
Not ALU Carry
ALU Overflow
Not ALU Overflow
MAC Overflow
Not MAC Overflow
X Input Sign Negative
X Input Sign Positive
Counter Expired
Always
True If:
AZ = 1
AZ = 0
AN .XOR. AV = 1
AN .XOR. AV = 0
(AN .XOR. AV) .OR. AZ = 1
(AN .XOR. AV) .OR. AZ = 0
AC = 1
AC = 0
AV = 1
AV = 0
MV = 1
MV = 0
AS = 1
AS = 0

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