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10 Memory Interface
This chapter includes example timing diagrams for the memory interfaces
of the ADSP-21xx processors. For each bus transaction, only the sequence
of events is described; you must consult the processor data sheets for
actual timing parameters. All timing diagrams use CLKOUT as a
reference, which indicates the instruction execution rate.
The memory interfaces of the ADSP-2181 are described separately in the
second half this chapter.
1x CLOCK
or
CRYSTAL
SERIAL
DEVICE
(OPTIONAL)
SERIAL
DEVICE
(OPTIONAL)
NOTES
1. Applies to all ADSP-21xx processors except ADSP-2181.
2. ADSP-2171 and ADSP-21msp58/59 use a 1/2x CLKIN signal.
3. Unused data bus lines may be left floating.
4. The two MSBs of the data bus (D23-22) are used to supply the two MSBs of the
boot memory EPROM address. This is only required for the 27256 and 27512.
Figure 10.1 ADSP-21xx System With External Memory
10 – 2
ADSP-21xx
ADDR
CLKIN
13-0
XTAL
CLKOUT
DATA
23-0
RESET
IRQ2
BR
BMS
BG
MMAP
SPORT 1
RD
WR
SCLK1
RFS1 or IRQ0
TFS1 or IRQ1
DT1 or FO
DR1 or FI
SPORT 0
SCLK0
PMS
RFS0
DMS
TFS0
DT0
DR0
A 13-0
14
D 23-22
D 15-8
24
A 13-0
D 23-0
A 13-0
D 23-8
BOOT
ADDR
MEMORY
DATA
e.g. EPROM
2764
OE
27128
27256
27512
CS
ADDR
PROGRAM
DATA
MEMORY
OE
(OPTIONAL)
WE
CS
ADDR
DATA
MEMORY
DATA
&
OE
PERIPHERALS
WE
CS
(OPTIONAL)
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