Configuration Example - Analog Devices adsp-2100 Manual

regardless of the source of frame sync signals; they either control the
polarity of internally generated signals or determine how externally
generated signals are interpreted.
The INVRFS bit is bit 6 in the SPORT control register (0x3FF6 for SPORT0
and 0x3FF2 for SPORT1), and the INVTFS bit is bit 7. These bits are both
cleared at reset, so that frame sync signals are active high.
5.8

CONFIGURATION EXAMPLE

The example code that follows illustrates how to configure the SPORTs.
This example configures both SPORT0 and SPORT1. SPORT0 is
configured for an internally generated serial clock (SCLK), internally
generated frame synchronization, and µ-law companded 8-bit data. This is
a typical setup for communication with a combo codec. SPORT1 is
configured for an externally generated serial clock, externally generated
frame synchronization, non-companded 16-bit data and autobuffering.
This setup could be used to transfer data between processors in a
multiprocessor system.
Only the needed memory mapped registers are initialized. Notice that the
SPORTs are configured before they are enabled and that any extraneous
latched interrupts are cleared before interrupts are enabled.
{—— SPORT INITIALIZATION CODE
{SPORT1 inits }
AX0 = 0x0017;
DM(0x3FEF) = AX0;
AX0 = 0x280F;
DM(0x3FF2) = AX0;
TFS}
bits}
Serial Ports
——}
{enable SPORT1 autobuffering}
{TX autobuffer uses I0 and M0}
{RX autobuffer uses I1 and M1}
{external serial clock, RFS and
{RFS and TFS are required, normal}
{framing, no companding and 16
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