Analog Devices adsp-2100 Manual page 328

Instruction Set Reference
The ADSP-2100 family processors can execute both data fetches and the
multiplication/accumulation in a single-cycle. Typically, a loop of
multiply/accumulates can be expressed in ADSP-21xx source code in just
two program lines. Since the on-chip program memory of the ADSP-21xx
processors is fast enough to provide an operand and the next instruction
in a single cycle, loops of this type can execute with sustained single-cycle
throughput. An example of such an instruction is:
MR=MR+MX0*MY0(SS), MX0=DM(I0,M0), MY0=PM(I4,M5);
The first clause of this instruction (up to the first comma) says that MR, the
MAC result register, gets the sum of its previous value plus the product of
the (current) X and Y input registers of the MAC (MX0 and MY0) both
treated as signed (SS).
In the second and third clauses of this multifunction instruction two new
operands are fetched. One is fetched from the data memory (DM) pointed
to by index register zero (I0, post modified by the value in M0) and the
other is fetched from the program memory location (PM) pointed to by I4
(post-modified by M5 in this instance). Note that indirect memory
addressing uses a syntax similar to array indexing, with DAG registers
providing the index values. Any I register may be paired with any M
register within the same DAG.
As discussed in Chapter 2, "Computational Units," registers are read at
the beginning of the cycle and written at the end of the cycle. The
operands present in the MX0 and MY0 registers at the beginning of the
instruction cycle are multiplied and added to the MAC result register, MR.
The new operands fetched at the end of this same instruction overwrite
the old operands after the multiplication has taken place and are available
for computation on the following cycle. You may, of course, load any data
registers in conjunction with the computation, not just MAC registers with
a MAC operation as in our example.
The computational part of this multifunction instruction may be any
unconditional ALU instruction except division or any MAC instruction
except saturation. Certain other restrictions apply: the next X operand
must be loaded into MX0 from data memory and the new Y operand must
be loaded into MY0 from program memory (internal and external memory
are identical at the level of the instruction set). The result of the
computation must go to the result register (MR or AR) not to the feedback
register (MF or AF).
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