Table of Contents
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Contents
12.1
12.1.1
12.1.1.1
12.1.2
12.1.2.1
12.1.2.2
12.1.2.3
12.1.2.4
12.1.3
12.1.4
12.1.5
12.1.6
12.1.7
12.1.8
12.1.9
12.2
12.2.1
12.2.2
13.1
13.2
13.3
13.4
13.5
13.6
13.7
14.1
14.2
14.3
14.4
14.5
14.6
14.7
14.7.1
14.7.2
14.7.3
14.7.4
x
OVERVIEW ...................................................................................... 12-1
Data Address Generators ......................................................... 12-2
Always Initialize L Registers ............................................. 12-2
Program Sequencer ................................................................... 12-4
Interrupts .............................................................................. 12-4
Loop Counts ......................................................................... 12-4
Status And Mode Bits.......................................................... 12-5
Stacks ..................................................................................... 12-5
Computational Units ................................................................. 12-6
Bus Exchange.............................................................................. 12-6
...................................................................................... 12-6
Serial Ports .................................................................................. 12-7
Memory Interface & SPORT Enables ...................................... 12-7
Host Interface ............................................................................. 12-8
Analog Interface ......................................................................... 12-8
PROGRAM EXAMPLE ................................................................... 12-8
Example Program: Setup Routine Discussion ..................... 12-10
Example Program: Interrupt Routine Discussion ............... 12-11
OVERVIEW ...................................................................................... 13-1
BOOT LOADING FROM HOST USING BUS REQUEST .......... 13-2
SERIAL PORT TO CODEC INTERFACE..................................... 13-5
SERIAL PORT TO DAC INTERFACE .......................................... 13-8
SERIAL PORT TO ADC INTERFACE ........................................ 13-10
SERIAL PORT TO SERIAL PORT INTERFACE ....................... 13-12
80C51 INTERFACE TO HOST INTERFACE PORT ................. 13-13
OVERVIEW ...................................................................................... 14-1
SYSTEM DEVELOPMENT PROCESS .......................................... 14-2
SINGLE-PRECISION FIR TRANSVERSAL FILTER .................. 14-4
CASCADED BIQUAD IIR FILTER ............................................... 14-6
SINE APPROXIMATION ............................................................... 14-7
SINGLE-PRECISION MATRIX MULTIPLY ................................ 14-9
RADIX-2 DECIMATION-IN-TIME FFT ..................................... 14-11
Main Module ............................................................................ 14-11
DIT FFT Subroutine ................................................................. 14-13
Bit-Reverse Subroutine ........................................................... 14-18
Block Floating-Point Scaling Subroutine .............................. 14-19
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