Contention For Companding Hardware; Companding Internal Data - Analog Devices adsp-2100 Manual

generates the transmit interrupt to indicate that TXn is ready for the next
data word. If the framing signal is being provided externally, the next
word must be written to TXn early enough to allow for compression
before the next framing signal arrives.
Here is a typical sequence of operations for receiving companded data:
• Bits accumulate as received in the internal receive register
• When a complete word is received, it is written to RXn
• The value in RXn is expanded
• The expanded value is written back to RXn
The receive interrupt for that SPORT is then generated.

5.10.2 Contention For Companding Hardware

Since both SPORTs share the companding hardware, only one
compression and one expansion operation can take place during a single
machine cycle. If contention arises, such as when two expansions need to
occur in the same cycle, SPORT0 has priority, while SPORT1 is forced to
wait one cycle.
The effects of contention, however, are usually small. The instruction set
does not support loading both TX0 and TX1 in the same cycle;
consequently these operations will be naturally out of phase for
contention in many cases. The overhead cycle for the receive operation
occurs prior to the receive interrupt and does not increase the time needed
to service the interrupt, although it does affect the latency prior to
receiving the interrupt.

5.10.3 Companding Internal Data

Because the values in the RX and TX registers are actually companded "in
place" it is possible to use the companding hardware internally, without
any transmission or reception at all and without enabling the serial port.
This operation can be used for debugging or data conversion and requires
a single cycle of overhead.
To compress data, enable companding and then:
1. Write data to TXn (compression is calculated).
2. Wait for one cycle (TXn is written with compressed value)
3. Read TXn (it returns the 8-bit compressed data)
Serial Ports 5
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