Alu Status; Multiplier/Accumulator (Mac); Mac Block Diagram Discussion - Analog Devices adsp-2100 Manual

2.2.8

ALU Status

The ALU status bits in the ASTAT register are defined below. Complete
information about the ASTAT register and specific bit mnemonics and
positions is provided in the Program Control chapter.
Flag Name
AZ Zero
AN Negative
AV Overflow
AC Carry
AS Sign
AQ Quotient
2.3

MULTIPLIER/ACCUMULATOR (MAC)

The multiplier/accumulator (MAC) provides high-speed multiplication,
multiplication with cumulative addition, multiplication with cumulative
subtraction, saturation and clear-to-zero functions. A feedback function allows
part of the accumulator output to be directly used as one of the multiplicands
on the next cycle.
2.3.1

MAC Block Diagram Discussion

Figure 2.6, on the following page, shows a block diagram of the multiplier/
accumulator.
The multiplier has two 16-bit input ports X and Y, and a 32-bit product output
port P. The 32-bit product is passed to a 40-bit adder/subtracter which adds
or subtracts the new product from the content of the multiplier result (MR)
register, or passes the new product directly to MR. The MR register is 40 bits
wide. In this manual, we refer to the entire register as MR. The register
actually consists of three smaller registers: MR0 and MR1 which are 16 bits
wide and MR2 which is 8 bits wide.
The adder/subtracter is greater than 32 bits to allow for intermediate overflow
in a series of multiply/accumulate operations. The multiply overflow (MV)
status bit is set when the accumulator has overflowed beyond the 32-bit
boundary, that is, when there are significant (non-sign) bits in the top nine bits
of the MR register (based on twos-complement arithmetic).
Computational Units
Definition
Logical NOR of all the bits in the ALU result register. True
if ALU output equals zero.
Sign bit of the ALU result. True if the ALU output is
negative.
Exclusive-OR of the carry outputs of the two most
significant adder stages. True if the ALU overflows.
Carry output from the most significant adder stage.
Sign bit of the ALU X input port. Affected only by the ABS
instruction.
Quotient bit generated only by the DIVS and DIVQ
instructions.
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