Divide - Analog Devices adsp-2100 Manual

ALU
15

DIVIDE

Z:
Xop:
Syntax:
Permissible xops
AX0
AX1
AR
Description:
divide primitives, DIVS and DIVQ. A single precision divide, with a 32-bit
numerator and a 16-bit denominator, yielding a 16-bit quotient, executes
in 16 cycles. Higher precision divides are also possible.
The division can be either signed or unsigned, but both the numerator and
denominator must be the same; both signed or unsigned. The programmer
sets up the divide by sorting the upper half of the numerator in any
permissible yop (AY1 or AF), the lower half of the numerator in AY0, and
the denominator in any permissible xop. The divide operation is then
executed with the divide primitives, DIVS and DIVQ. Repeated execution
of DIVQ implements a non-restoring conditional add-subtract division
algorithm. At the conclusion of the divide operation the quotient will be in
AY0.
To implement a signed divide, first execute the DIVS instruction once,
which computes the sign of the quotient. Then execute the DIVQ
instruction for as many times as there are bits remaining in the quotient
(e.g., for a signed, single-precision divide, execute DIVS once and DIVQ 15
times).
To implement an unsigned divide, first place the upper half of the
numerator in AF, then set the AQ bit to zero by manually clearing it in the
Arithmetic Status Register, ASTAT. This indicates that the sign of the
quotient is positive. Then execute the DIVQ instruction for as many times
as there are bits in the quotient (e.g., for an unsigned single-precision
divide, execute DIVQ 16 times).
15 – 38
Destination register
X operand
DIVS yop , xop ;
DIVQ xop ;
Permissible yops
MR2 AY1
MR1 AF
MR0
SR1
SR0
These instructions implement yop ÷ xop. There are two
Yop: Y operand
COND: condition