Analog Devices adsp-2100 Manual page 72

3 Program Control
Because of the efficient stack and program sequencer, there is no latency
(beyond synchronization delay) when processing unmasked interrupts,
even when interrupting DO UNTIL loops. Nesting of interrupts allows
higher-priority interrupts to interrupt any lower-priority interrupt service
routines that may currently be executing, also with no additional latency.
The ADSP-2100 family processors include a secondary register set which
can be used to provide a fresh set of ALU, MAC, and Shifter registers
during interrupt servicing. This feature allows single-cycle context
switching. Use of the secondary registers is described in the "Mode Status
Register (MSTAT)" section of this chapter.
Interrupt Source
RESET
IRQ2
SPORT0 Transmit
SPORT0 Receive
SPORT1 Transmit or IRQ1
SPORT1 Receive or IRQ0
Timer
Table 3.2 ADSP-2101/2115 Interrupts & Interrupt Vector Addresses
Interrupt Source
RESET startup
IRQ2
SPORT1 Transmit or IRQ1
SPORT1 Receive or IRQ0
Timer
Table 3.3 ADSP-2105 Interrupts & Interrupt Vector Addresses
Interrupt Source
RESET startup
IRQ2
HIP Write (from Host)
HIP Read (to Host)
SPORT0 Transmit
SPORT0 Receive
SPORT1 Transmit or IRQ1
SPORT1 Receive or IRQ0
Timer
Table 3.4 ADSP-2111 Interrupts & Interrupt Vector Addresses
3 – 12
startup
Interrupt Vector Address
0x0000
0x0004 (highest priority)
0x0008
0x000C
0x0010
0x0014
0x0018 (lowest priority)
Interrupt Vector Address
0x0000
0x0004 (highest priority)
0x0010
0x0014
0x0018 (lowest priority)
Interrupt Vector Address
0x0000
0x0004 (highest priority)
0x0008
0x000C
0x0010
0x0014
0x0018
0x001C
0x0020 (lowest priority)