Adsp-2181 Program Memory Interface - Analog Devices adsp-2100 Manual

Unlike other processors of the ADSP-2100 family, the ADSP-2181 supports
several additional memory interfacing features. These features include:
• External Overlay Memory in 8K segments: these segments can be
swapped for the upper 8K of internal program memory or lower 8K of
data memory.
• I/O Memory space: this memory space is for peripheral I/O, has 2K
(16-bit wide) locations, and has four user-assignable waitstate ranges.
• Byte Memory & Byte Memory DMA (BDMA): this memory space can
address up to 4M bytes. The byte memory interface supports booting
from and runtime access to inexpensive 8-bit memories. The DMA
feature lets you define the number of memory locations the DSP will
transfer to/from internal memory in the background while continuing
foreground processing.
• Internal Direct Memory Access (IDMA) Port: this port supports booting
from and runtime access to host systems (for example, PC Bus Interface
ASICs). The DMA feature of this port lets you define the number of
memory locations the DSP will transfer to/from internal memory in the
background while continuing foreground processing.
For complete information on the BDMA port, including booting, and IDMA
port, refer to the DMA Ports chapter of this manual.
The ADSP-2181 uses a half-instruction-rate clock input from which it
generates a full-instruction-rate internal clock. For example, from a
16.67 MHz clock input (CLKIN) the ADSP-2181 generates a 33.33 MHz
instruction rate clock. All timing diagrams for the processor use the full-
instruction-rate output clock (CLKOUT) as a reference.
All external memories may have automatic wait state generation associated
with them. The number of wait states—each equal to one instruction cycle—
is programmable.
10.6.1

ADSP-2181 Program Memory Interface

The ADSP-2181 processor addresses its 16K of internal program memory as
well as two 8K external program memory overlays. All program memory is
24 bits wide. Up to two accesses to internal program memory can be
completed per instruction cycle; this lets the DSP complete all operations in
a single cycle. The PWAIT field of the System Control Register (shown in
Figure 10.24) sets the number of waitstates for each access to program
memory overlays. PWAIT defaults (after reset) to seven.
Memory Interface 10
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