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5 Serial Ports
are cleared at reset, disabling both SPORTs.
Bit 10 of the system control register determines the configuration of
SPORT1, either as a serial port or as interrupts and flags, according to
Table 5.4 on the next page. If bit 10 is a 1, SPORT1 operates as a serial port;
if it is a 0, the alternate functions are in effect (and bit 11 is ignored). At
reset, bit 10 is a 1, so SPORT1 functions as a serial port.
Pin Name
RFS1
TFS1
DR1
DT1
SCLK1
Table 5.4 SPORT1 Alternate Configuration
5.5
Each SPORT operates on its own serial clock signal. The serial clock
(SCLK) can be internally generated or received from an external source.
The ISCLK bit, bit 14 in either the SPORT0 or SPORT1 control register,
determines the SCLK source for the SPORT. If this bit is a 1, the processor
generates the SCLK signal; if it is a 0, the processor expects to receive an
external clock signal on SCLK. At reset, ISCLK is cleared, so both serial
ports are in the external clock mode. When ISCLK is set, internal
generation of the SCLK signal begins on the next instruction cycle,
whether or not the corresponding SPORT is enabled.
15
14
ISCLK
Figure 5.3 ISCLK Bit In SPORT Control Register
5 – 8
Alternate Name
IRQ0
IRQ1
FI
FO
Same
SPORT0 Control Register: 0x3FF6
SPORT1 Control Register: 0x3FF2
13
12
11
10
9
0 = External (Default)
1 = Internal
Alternate Function
External interrupt 0
External interrupt 1
Flag input
Flag output
Same
SERIAL CLOCKS
8
7
6
5
4
3
2
1
0
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