Hip Status Synchronization - Analog Devices adsp-2100 Manual

7 Host Interface Port
For example, the ADSP-21xx can wait in a loop reading an HSR bit to see
if the host has written new data. When the ADSP-21xx sees that the bit is
set, it conditionally jumps out of the loop, processes the new data, then
returns to the loop. When transferring data to the host, the ADSP-21xx
waits for the host to read the last data written so that new data can be
transferred. The host polls the HSR bits to see when the new data is
available.

7.4.1.1 HIP Status Synchronization

Processes running on the ADSP-21xx are asynchronous to processes
running on the host. Values in the shared status registers (HSR6, HSR7)
can therefore change at any time, and reading a changing value could give
unpredictable results. The ADSP-21xx HIP, however, includes
synchronization circuitry which guarantees that the HIP status is constant
during a read by either the ADSP-21xx core or the host. This
synchronization is illustrated in Figures 7.3 and 7.4. The status registers
are updated by the ADSP-21xx and thus are synchronous with the ADSP-
21xx processor clock, but host accesses are asynchronous with respect to
the ADSP-21xx clock.
When the host reads HSR6 or HSR7 to obtain status information, there is a
one-cycle synchronization delay before the current (i.e. updated) status is
available. To obtain the correct, current status, therefore, the host must perform
HCLK
d1
status
change
Figure 7.3 Host Status Synchronization
CLKOUT
d1 status
change
Figure 7.4 ADSP-21xx HIP Status Synchronization
7 – 8
Host
Access
d2 c1
status host status
change update
d2 status c1
change
c2
21xx HIP
status update
Host
Access
c2
host status
update
21xx HIP
status update