Short Write Cycle - Analog Devices adsp-2100 Manual

11.3.4.5 Short Write Cycle

The host writes the contents of a ADSP-2181 internal memory location using the
IDMA short write cycle. The write cycle, shown in Figure 11.13, consists of the
following steps:
1. Host ensures that
IWR
2. Host asserts
the IAD15-0 address/data bus to the location pointed to by the target IDMA
address .
3. ADSP-2181 deasserts
write operation.
4. Host drives the data on the IAD address/data bus.
IWR
5. Host deasserts
(ending the short write cycle).
6. ADSP-2181 detects
IAD address/data bus.
7. Host stops driving the data on the IAD15-0 address/data bus after meeting
the short write timing requirements.
Note that IAL is low (inactive) and IRD is high (inactive) throughout the write
operation.
IACK
IS
IWR
IAD15-0
Figure 11.13 IDMA Short Write Cycle Timing
IACK
line is low.
IS
and (low), directing the ADSP-2181 to write the data on
IACK
line (high), indicating it recognizes the IDMA
IS
and after meeting the short write timing requirements
and have gone high, then latches the data on the
IWR IS
DATA
DMA Ports 11
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