Analog Devices adsp-2100 Manual page 126

the overhead cycle. A delay in the autobuffer transfer occurs if the transfer
is required during an instruction executing in multiple cycles (for wait
states, for example). If the transfer is required when the processor is
waiting in an IDLE state, the transfer is executed and the processor returns
to IDLE.
When a data word transfer causes the circular buffer pointer to wrap
around, the SPORT interrupt is generated. The receive interrupt occurs
after the complete buffer has been received. The transmit interrupt occurs
when the last word is loaded into TXn, prior to transmission.
Aside from the completion of an instruction requiring multiple cycles, the
automatic transfer of individual data words has the highest priority of any
operation short of RESET, including all interrupts. Thus, it is possible for
an autobuffer transfer to increase the latency of an interrupt response if
the interrupt happens to coincide with the transfer. Up to four
autobuffered transfers can occur; in the case that two or more are needed
in the same cycle, they have the following priority, which is the same as
the SPORT interrupt priority:
Highest SPORT0 Transmit
SPORT0 Receive
SPORT1 Transmit
Lowest SPORT1 Receive
SPORT0 Autobuffer Control Register: 0x3FF3
SPORT1 Autobuffer Control Register: 0x3FEF
15 14 13 12 11
Figure 5.23 SPORT Autobuffer Control Register
Serial Ports
10 9 8 7
TIREG TMREG
(Transmit Autobuffering Enable)
6 5 4 3 2
RIREG RMREG
(Receive Autobuffering Enable)
5
1 0
TBUF
RBUF
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