Adc & Dac Interrupts; Autobuffering Disabled - Analog Devices adsp-2100 Manual

8 Analog Interface
8.4.3
The analog interface generates two interrupts that signal either:
1) that a 16-bit, 8 kHz analog-to-digital or digital-to-analog conversion
has been completed, or 2) that an autobuffer block transfer has been
completed (i.e. the entire data buffer contents have been transmitted or
received).
When one of the analog interrupts occurs, the processor vectors to the
appropriate address:
DAC Transmit interrupt vector address:
ADC Receive interrupt vector address:
These interrupts can be masked out in the processor's IMASK register
and can be forced or cleared in the IFC register.

8.4.3.1 Autobuffering Disabled

The ADC receive and DAC transmit interrupts occur at an 8 kHz rate,
indicating when the data registers should be accessed, when
autobuffering is disabled. On the receive side, the ADC interrupt is
generated each time an A/D conversion cycle is completed and the
16-bit data word is available in the ADC receive register. On the
transmit side, the DAC interrupt is generated each time a D/A
conversion cycle is completed and the DAC transmit register is ready
for the next 16-bit data word.
Both interrupts are generated simultaneously at an 8 kHz rate,
occurring every 3250 instruction cycles with a 13 MHz internal clock,
when autobuffering is disabled. The interrupts are generated
continuously, starting when the analog interface is powered up by
setting the APWD bits (bits 5, 6) to ones in the analog control register.
Because both interrupts occur simultaneously, only one should be
enabled (in IMASK) to vector to a single service routine that handles
both transmit and receive data. (When autobuffering is enabled,
though, both interrupts should be enabled.)
A simple analog loopback program is shown in Listing 8.1.
8 – 12
ADC & DAC Interrupts
0x18
0x1C