Biased Rounding (Adsp-217X/218X/21Msp5X) - Analog Devices adsp-2100 Manual

Example 2
Unrounded value:
Bit 15 = 1 and bits 0-14 = 0
Add 1 to bit 15 and carry
Since bit 16 = 1, force it to 0
Rounded value:
In this last case, bit 16 is forced to zero. This algorithm is employed on every
rounding operation, but is only evident when the bit patterns shown in the
lower 16 bits of the last example are present.
2.3.2.7 Biased Rounding (ADSP-217x, ADSP-218x, ADSP-21msp5x)
A mode is available on the ADSP-217x, ADSP-218x, and ADSP-21msp58/
59 processors to allow biased rounding in addition to the normal unbiased
rounding. This mode is selected by the BIASRND bit (bit 12 of the SPORT0
Autobuffer Control register). When the BIASRND bit is set to 0, the normal
unbiased rounding operations occur. When the BIASRND bit is set to 1,
biased rounding occurs instead of the normal unbiased rounding. When
operating in biased rounding mode all rounding operations with MR0 set
to 0x8000 will round up, rather than only rounding odd MR1 values up.
For example:
MR value before RND
00-0000-8000
00-0001-8000
00-0000-8001
00-0001-8001
00-0000-7FFF
00-0001-7FFF
This mode only has an effect when the MR0 register contains 0x8000; all
other rounding operations work normally. This mode allows more efficient
implementation of bit-specified algorithms that use biased rounding, for
example the GSM speech compression routines. Unbiased rounding is
preferred for most algorithms.
Computational Units
MR2 MR1
xxxxxxxx xxxxxxxx01100110 1000000000000000
xxxxxxxx xxxxxxxx01100111 0000000000000000
xxxxxxxx xxxxxxxx01100110 0000000000000000
biased RND result
00-0001-8000
00-0002-8000
00-0001-8001
00-0002-8001
00-0000-7FFF
00-0001-7FFF
MR0
1
unbiased RND result
00-0000-8000
00-0002-8000
00-0001-8001
00-0002-8001
00-0000-7FFF
00-0001-7FFF
2
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