Analog Devices adsp-2100 Manual page 6

Contents
CHAPTER 9
9.1
9.2
9.2.1
9.2.2
9.3
9.4
9.4.1
9.5
9.5.1
9.6
9.7
9.7.1
9.7.2
9.7.3
9.7.3.1
9.7.3.2
9.7.4
9.7.4.1
9.7.4.2
9.7.5
9.7.5.1
9.7.5.2
9.7.5.3
9.7.5.4
9.7.5.5
9.7.5.6
9.7.6
9.7.7
9.7.8
CHAPTER 10
10.1
10.2
10.2.1
10.2.2
10.2.3
10.3
10.3.1
10.3.2
10.3.3
viii
SYSTEM INTERFACE
OVERVIEW ........................................................................................ 9-1
CLOCK SIGNALS.............................................................................. 9-3
Synchronization Delay ................................................................ 9-3
1x & 1/2x Clock Considerations ............................................... 9-4
RESET ........................................................................................ 9-4
SOFTWARE-FORCED REBOOTING ............................................. 9-4
ADSP-2181 Register Values For BDMA Booting .................. 9-13
EXTERNAL INTERRUPTS ............................................................. 9-14
Interrupt Sensitivity .................................................................. 9-14
FLAG PINS ...................................................................................... 9-15
POWERDOWN ................................................................................ 9-17
Powerdown Control .................................................................. 9-18
Entering Powerdown ................................................................ 9-19
Exiting Powerdown ................................................................... 9-20
Ending Powerdown With The
Ending Powerdown With The
Startup Time After Powerdown .............................................. 9-21
Systems Using An External TTL/CMOS Clock .............. 9-21
Systems Using A Crystal/Internal Oscillator .................. 9-22
Operation During Powerdown ................................................ 9-23
Interrupts & Flags ................................................................ 9-23
SPORTS ................................................................................. 9-23
HIP During Powerdown..................................................... 9-24
IDMA Port During Powerdown (ADSP-2181) ................ 9-25
BDMA Port During Powerdown (ADSP-2181) ............... 9-26
Analog Interface (ADSP-21msp5x) ................................... 9-26
Conditions For Lowest Power Consumption ........................ 9-26
PWDACK Pin ............................................................................. 9-29
Using Powerdown As A Non-Maskable Interrupt ............... 9-30
MEMORY INTERFACE
OVERVIEW ...................................................................................... 10-1
PROGRAM MEMORY INTERFACE ............................................ 10-3
External Program Memory Read/Write ................................ 10-3
Program Memory Maps............................................................ 10-5
ROM Program Memory Maps ................................................. 10-6
DATA MEMORY INTERFACE ................................................... 10-10
External Data Memory Read/Write ..................................... 10-10
Data Memory Maps ................................................................. 10-11
Memory-Mapped Peripherals................................................ 10-14
Pin .......................... 9-20
PWD
Pin ....................... 9-21
RESET