Adsp-2181 Data Memory Interface - Analog Devices adsp-2100 Manual

10 Memory Interface
contents of PMOVLAY as part of your interrupt service routine.
10.6.2
The ADSP-2181 addresses 16K x 16-bit wide internal data memory and
two 8K x 16-bit wide external data memory overlays. All accesses to
internal data memory are completed in a single processor instruction
cycle. The DWAIT field of the Waitstate Control Register (shown in Figure
10.28) sets the number of waitstates for each access to data memory
overlays. Figure 10.29 shows the data memory map of the ADSP-2181.
The processor's memory-mapped control/status registers are mapped
into the top locations of internal data memory, addresses 0x3FE0-0x3FFF.
Most of the ADSP-2181's control registers correspond to those found on
other ADSP-21xx processors. Note that the ADSP-2181's System Control
Register does not have the boot memory control fields found on other
ADSP-21xx processors. Also note that the Waitstate Control Register
15 14
0
Figure 10.28 ADSP-2181 Wait State Control Register
Data Memory
32 Memory-Mapped
Control Registers
8160 words
8K Internal
(DMOVLAY=0)
External 8K
(DMOVLAY=1,2)
Figure 10.29 ADSP-2181 Data Memory Map
10 – 30

ADSP-2181 Data Memory Interface

Wait State Control Register
13 12 11 10
1 1 1 1 1
DWAIT IOWAIT3
Address
0x3FFF
0x3FE0
0x3FDF
Internal
0x2000
0x1FFF
or
0x0000
9 8 7 6 5
1 1 1 1 1
IOWAIT2 IOWAIT1
4 3 2 1 0
1 1 1 1 1
IOWAIT0
DM(0x3FFE)